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A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture

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6 Author(s)
Fukaishi, M. ; System ULSI Res. Lab., NEC Corp., Kanagawa, Japan ; Nakamura, K. ; Sato, M. ; Tsutsui, Y.
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A single-chip 1.25-Gb/s 32:1, 1:32 transceiver, as specified in the emerging American National Standards Institute fiber channel standard, has been developed using 0.25-μm CMOS technology. Newly developed features contributing to the achievement of 4.25-Gb/s operations include: 1) an asynchronous tree-type 1:8 demultiplexer, 2) an 8-10 bit parallel-to-parallel frequency conversion circuit, and 3) comma detection and word alignment logic. The transceiver consumes 600 mW in 4.25-Gb/s operations with a 2.5 V supply. This design helps achieve higher speed operations and only half the power dissipation of the fastest previously reported CMOS fiber channel design that includes an 8B10B encoder and a 10B8B decoder

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Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 12 )