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A 400-Msample/s, 6-b CMOS folding and interpolating ADC

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2 Author(s)
M. P. Flynn ; DSPS R&D Lab., Texas Instrum. Inc., Dallas, TX, USA ; B. Sheahan

A 400-Msample/s, 6-bit CMOS folding and interpolating analog-to-digital converter (ADC) is described. A low-impedance current-mode approach is adopted. Current-division interpolation incorporated within the folders allows fast operation and is compatible with low supply voltages. This interpolation scheme, together with a short aperture comparator, gives good performance for input frequencies up to one-quarter of the sampling rate without using a sample and hold. For simplicity, the ADC uses only a single clock and its complement. The device is implemented in a 0.5 μm BiCMOS technology using only CMOS devices. The converter occupies 0.6 mm2 and dissipates 200 mW from a 3.2 V supply

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 12 )