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A digital background calibration technique for time-interleaved analog-to-digital converters

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4 Author(s)
Fu, D. ; California Univ., Davis, CA, USA ; Dyer, K.C. ; Lewis, S.H. ; Hurst, P.J.

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 μm CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm2, and the power dissipation is 565 mW from a 5 V supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 12 )