A third-order /spl Delta/-/spl Sigma/ modulator using second-order noise-shaping dynamic element matching

A multibit /spl Delta/-/spl Sigma/ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit /spl Delta/-/spl Sigma/ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a /spl Delta/-/spl Sigma/ ADC and DAC using the second-order NSDEM method. The test chip of the third-order /spl Delta/-/spl Sigma/ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply.