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Low-power multirate architecture for IF digital frequency down converter

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3 Author(s)
Shyh-Jye Jou, ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; Shou-Yang Wu ; Chorng-Kuang Wang

In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-IF oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on the multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. The design example shows that it consumes only 24% of the power of the direct implementation while occupying 26% less area

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:45 ,  Issue: 11 )

Date of Publication:

Nov 1998

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