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CAD-oriented equivalent circuit modeling of on-chip interconnects in CMOS technology

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6 Author(s)
Zheng, J. ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Tripathi, A. ; Hahm, Y.C. ; Ishii, T.
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A CAD-oriented modeling methodology for on-chip interconnects on lossy substrates in CMOS technology, which is based on quasistatic EM analysis and equivalent circuit model extraction, is presented. The frequency response of the equivalent circuit model shows good agreement with the computed quasi-static solution over the entire frequency range of interest. The model is further validated by comparison with the interconnect step response

Published in:

Electrical Performance of Electronic Packaging, 1998. IEEE 7th Topical Meeting on

Date of Conference:

26-28 Oct 1998