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Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems

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5 Author(s)
D'Angelo, S. ; Ist. di Fisica Cosmica, CNR, Milano, Italy ; Metra, C. ; Pastore, S. ; Pogutz, A.
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This paper presents an original approach to the implementation of a fault-tolerant FPGA-based system. In particular, we consider the conventional Triple Modular Redundancy fault-tolerance technique and address practical problems related to its actual implementation into FPGA devices. All possible functional faults affecting the used FPGAs are either tolerated or on-line detected. Differently from conventional VLSI fault-tolerant systems, here the FPGA possible reconfigurability is exploited to ensure the continuity of operation for a high number of possible internal faults, without requiring further replications (besides the three basic copies) of the considered device

Published in:

Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on

Date of Conference:

2-4 Nov 1998