Referenced Items are not available for this document.
This paper reports a yield model applied to a large set of defectivity data measured on a 0.35 micron process in ST Crolles plant and critical areas extracted by survey sampling. It takes into account all defect densities measured at the main process steps and determines their respective yield loss. The robustness of the model was tested week by week during three months of production for two high volume devices. The model was then applied wafer by wafer on a new process version
Published in:
Defect and Fault Tolerance in VLSI Systems, 1998. Proceedings., 1998 IEEE International Symposium on
Date of Conference: 2-4 Nov 1998
- Page(s):
- 17 - 25
- Meeting Date :
- 02 Nov 1998-04 Nov 1998
- ISSN :
- 1063-6722
- Print ISBN:
- 0-8186-8832-7
- INSPEC Accession Number:
- 6214838
- Conference Location :
- Austin, TX
- Digital Object Identifier :
- 10.1109/DFTVS.1998.732147
- Product Type:
- Conference Publications
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