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Sub-0.25-micron interconnection scaling: damascene copper versus subtractive aluminum

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3 Author(s)
Stamper, A.K. ; IBM Corp., Essex Junction, VT, USA ; McDevitt, T.L. ; Luce, S.L.

Historically, the semiconductor industry has made chip speed the focus of its high performance CMOS logic development strategy. For the wires and insulators used in the back-end-of-the-line (BEOL), this has driven the industry to use damascene tungsten chemical-mechanical polish (CMP) local interconnects and vias; SiO2-based intermetal dielectric CMP planarization; high-aspect ratio aluminum wiring; high density plasma, ozone/TEOS, or advanced spin-on glass SiO2 intermetal dielectrics; high density plasma reactive ion etching; and excimer-laser DUV lithography. In order to achieve 0.25 μm CMOS performance objectives, the aluminum wire and tungsten via aspect ratios have increased by about a factor of two as compared to 0.50 μm CMOS. This aggressive reverse scaling of BEOL dimensions increases the defect and yield issues associated with the industry standard subtractive-aluminum etch process. We believe that, if subtractive-aluminum wiring is used, the additional scaling required to meet the performance targets of sub-0.25 μm CMOS logic will result in significantly lower yields and increased manufacturing costs. Rather than attempt to drive subtractive-aluminum wiring beyond its reasonable limits, IBM has chosen to employ an additive-copper dual-damascene wiring process for its high performance sub-0.25 μm CMOS logic technologies. In this paper, we discuss defect density, resistance variability, and capacitance variability for 0.25 μm and 0.18 μm CMOS generation subtractive-aluminum and damascene copper wiring

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI

Date of Conference:

23-25 Sep 1998

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