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40 nm gate length ultra-thin SOI n-MOSFETs with a backside conducting layer

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6 Author(s)
Suzuki, E. ; Electrotech. Lab., Ibaraki, Japan ; Ishii, K. ; Kanemaru, S. ; Maeda, T.
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There has been intensive interest in how far Si MOSFETs can be scaled in future VLSIs. Although the short channel effect becomes severe with decreasing channel length, modelling and simulation have indicated still wide room even beyond 0.1 /spl mu/m Si technologies (Sekigawa and Hayashi, 1984, and Yan et al., 1992). To avoid the short channel and punch-through effects in such short channel devices, it has been pointed out that a thin active Si layer with a backside conducting layer and an ultra-shallow source and drain junction are effective. In this paper, we demonstrate the high performance of 40 nm gate length ultra-thin SOI n-MOSFETs with a 100 nm buried oxide and a backside conducting layer, and confirm the excellent roll-off characteristics.

Published in:

Device Research Conference Digest, 1998. 56th Annual

Date of Conference:

22-24 June 1998

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