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Clock switching: a new design for current testability (DcT) method for dynamic logic circuits

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5 Author(s)
Rosing, R. ; Microelectron. Res. Group, Lancaster Univ., UK ; Richardson, A.M.D. ; Aimine, Y.E. ; Kerkhoff, H.G.
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Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults

Published in:

IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on

Date of Conference:

12-13 Nov 1998