Skip to Main Content
Advances in lithography and thinner SiO2 gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta2O5, have been suggested as a substitute for SiO2 as the gate material beyond t/sub ox//spl ap/25 /spl Aring/. However, the Si-Ta2O5 material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. We present a solution to these issues through a novel synthesis of a thermally grown SiO2(10 /spl Aring/)-Ta2O5 (MOCVD-50 /spl Aring/)-SiO2 (LPCVD-5 /spl Aring/) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents.