MOS transistors with stacked SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/ gate dielectrics for giga-scale integration of CMOS technologies

Advances in lithography and thinner SiO/sub 2/ gate oxides have enabled the scaling of MOS technologies to sub-0.25-/spl mu/m feature size. High dielectric constant materials, such as Ta/sub 2/O/sub 5/, have been suggested as a substitute for SiO/sub 2/ as the gate material beyond t/sub ox//spl ap/25 /spl Aring/. However, the Si-Ta/sub 2/O/sub 5/ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO/sub 2/(10 /spl Aring/)-Ta/sub 2/O/sub 5/ (MOCVD-50 /spl Aring/)-SiO/sub 2/ (LPCVD-5 /spl Aring/) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents.