MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration of CMOS technologies

Advances in lithography and thinner SiO
₂
gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta
₂
O
₅
, have been suggested as a substitute for SiO
₂
as the gate material beyond t/sub ox//spl ap/25 /spl Aring/. However, the Si-Ta
₂
O
₅
material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. We present a solution to these issues through a novel synthesis of a thermally grown SiO
₂
(10 /spl Aring/)-Ta
₂
O
₅
(MOCVD-50 /spl Aring/)-SiO
₂
(LPCVD-5 /spl Aring/) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents.