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Simulating the impact of pattern-dependent poly-CD variation on circuit performance

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5 Author(s)
Stine, B.E. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Boning, D.S. ; Chung, J.E. ; Ciplickas, D.J.
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In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 μm 64×8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:11 ,  Issue: 4 )

Date of Publication:

Nov 1998

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