Referenced Items are not available for this document.
In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 μm 64×8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:11
,
Issue:
4
)
Date of Publication: Nov 1998
- Page(s):
- 552 - 556
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 6094350
- Digital Object Identifier :
- 10.1109/66.728551
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1998
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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