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A fast interrupt handling scheme for VLIW processors

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6 Author(s)
Ozer, E. ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; Sathaye, S.W. ; Menezes, K.N. ; Banerjia, S.
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Interrupt handling in out-of-order execution processors requires complex hardware schemes to maintain the sequential state. The amount of hardware will be substantial in VLIW architectures due to the nature of issuing a very large number of instructions in each cycle. It is hard to implement precise interrupts in out-of-order execution machines, especially in VLIW processors. In this paper, we will apply the reorder buffer with future file and the history buffer methods to a VLIW platform, and present a novel scheme, called the current-state buffer, which employs modest hardware with compiler support. Unlike the other interrupt handling schemes, the current-state buffer does not keep history state, result buffering or bypass mechanisms. It is a fast interrupt handling scheme with a relatively small buffer that records the execution and exception status of operations. It is suitable for embedded processors that require a fast interrupt handling mechanism with modest hardware

Published in:

Parallel Architectures and Compilation Techniques, 1998. Proceedings. 1998 International Conference on

Date of Conference:

12-18 Oct 1998