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Fast low-power shared division and square-root architecture

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2 Author(s)
Kuhlmann, M. ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA ; Parhi, K.K.

This paper addresses a fast low-power implementation of a shared division and square-root architecture. Two approaches are considered in this paper; these include the SRT (Sweeney, Robertson and Tocher) approach which does not require prescaling and the GST (generalized Svoboda and Tung) approach which requires prescaling of the operands. This paper makes two important contributions. Although SRT division and square-root approaches and GST division approach have been known for long time, square-root architectures based on the GST approach have not been proposed so far. This paper for the first time, develops a GST square-root architecture without requiring an additional division by the scaling factor after the square-root operation. Although various divider and square-root architectures have been compared with respect to speed, no tradeoffs with respect to power consumption of these architectures have been studied so far quantitative comparison of speed and power consumption of GST and SRT division/square-root units is the second main contribution of the paper. Shared divider and square-root units are designed based on the SRT and the GST approaches, in both minimally and maximally redundant radix-4 representations. Simulations demonstrate that the worst-case overall latency of the minimally-redundant GST architecture is 35% smaller compared to the SRT. Alternatively, for a fixed latency, the minimally-redundant GST architecture based division and square-root operations consume 42% and 20% less power respectively, compared to the maximally-redundant SRT approach

Published in:

Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on

Date of Conference:

5-7 Oct 1998