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System-level performance estimation strategy for sw and hw

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5 Author(s)
A. Allara ; Central Res. Labs., ITALTEL, Italy ; C. Brandolese ; W. Fornaciari ; F. Salice
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The design of an embedded system is a process where the tuning of the architecture should take into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device

Published in:

Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on

Date of Conference:

5-7 Oct 1998