By Topic

Design of integrated DSP solution for cardiologic problems using revolutionary VLSI methodologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Vandenbogaerde, H. ; Catholic Inst. of Technol., Ostend, Belgium ; Verbeke, J. ; Vanneuville, J. ; Sinnaeve, A.
more authors

The authors describe the application of the Cathedral silicon compiler (J. Rabaey et al. 1988) to the design of digital signal processors (DSPs) for cardiological data. Cathedral 1 permits the automated synthesis, analysis, optimization, and simulation of wave digital filters, while Cathedral 2 automates the design of multiprocessor DSP systems. Starting from an algorithmic description, interactive optimization leads to the generation of an optimal integrated circuit layout. The authors used the design tools to implement automatic defibrillation, antitachy, and cardioversion building blocks, i.e. linear and nonlinear ECG filtering, QRS detection using adaptive thresholds, and recognition of ventricular arrhythmia using the probability-density function of the ECG and autocorrelation of both ECG and intramyocardial pressure. Preliminary simulation results show good parameter discrimination performance

Published in:

Computers in Cardiology, 1988. Proceedings.

Date of Conference:

25-28 Sep 1988