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A high-speed, low-power clock generator for a microprocessor application

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1 Author(s)
V. R. von Kaenel ; Compaq Comput. Corp., Palo Alto, CA, USA

This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 μm process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than ±100 ps

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 11 )