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A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects

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18 Author(s)
Akrout, C. ; Microelectron. Div., IBM Corp., Austin, TX, USA ; Bialas, J. ; Canada, M. ; Cawthron, D.
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This paper describes the performance improvements of a reduced instruction set computer (RISC) microprocessor that has migrated from a 2.5 V technology to a 1.8 V technology. The 1.8 V technology implements copper interconnects and low Vt field-effect transistors in speed-critical paths and has an Leff of 0.12 μm. Global clock latency and skew are improved by using copper wires, and early mode timings are improved by reducing clock skew and adding buffers. These enhancements, along with an environment of 2.0 V, 85°C, and with a fast process, produced a 480-MHz RISC microprocessor

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 11 )

Date of Publication:

Nov 1998

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