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A fast sequential learning technique for real circuits with application to enhancing ATPG performance

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3 Author(s)
El-Maleh, A. ; Mentor Graphics Corp., Beaverton, OR, USA ; Kassab, M. ; Rajski, J.

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.

Published in:

Design Automation Conference, 1998. Proceedings

Date of Conference:

19-19 June 1998

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