Application of moire interferometry in electronics packaging

The presence of thermally induced stresses due to coefficient of thermal expansion (CTE) mismatch of different materials in electronic packaging is an intrinsic issue. These stresses often result in delamination at the interfaces of different materials, thereby causing reliability concerns. The moire interferometry technique has been increasingly used in mapping thermally induced deformation of electronic packages. Its high displacement measurement sensitivity allows the global deformation of packages with complex geometry to be determined. These deformation fields allow the strains induced in the package to be computed to provide an indication of the level of stresses. In this paper, thermally induced deformation of different types of electronic packages, such as BGAs, CSPs and flip-chip assemblies, have been studied by the moire interferometry technique. Deformation patterns before and after surface mounting on PCBs were also investigated. These patterns allow the relative displacement within the packages and the high strain regions to be determined. As such, a better understanding of the stresses induced in the package due to CTE mismatch can be obtained. The study also includes the cumulative effect of deformation in different packages caused by temperature cycling. The deformation patterns clearly indicate the high strain regions at the package interconnection location as a result of this cyclic loading. These methods allow a more accurate and realistic understanding of macro-mechanical behaviour of packaging assembly and interconnections.