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Two of the most serious issues for thin film SOI CMOS are the high source/drain series resistance and the floating body effect. In the past, we have demonstrated that a Ge preamorphization can be used to control the salicide depth. It suppresses void formation, which often occurs in conventional thin film SOI silicide processes, and reduces the floating body effect (Hsiao et al., 1997). More recently, we proposed a Ge large angle tilt implant (LATI) as an approach to further reduce the floating body effect (Hsiao et al., 1997). In this paper, we present an optimized low thermal budget salicide process and detailed characterization of SOI devices with Ge LATI.