Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Effect of body-to-source bias on the analog characteristics of 0.35 /spl mu/m partially depleted SOI CMOS for low-voltage low-power mixed-mode applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Babcock, J.A. ; Nat. Semicond. Corp., Santa Clara, CA, USA ; Francis, P. ; Haggag, H. ; Darmawan, J.
more authors

A 3.3 V 0.35 /spl mu/m CMOS process, implemented on 8-inch bonded SOI wafers, is investigated for low-voltage low-power analog applications. Enhanced low-power analog performance is demonstrated by applying a forward biased body-source voltage which enables reduced short channel effects and a flatter threshold voltage response as a function of drawn gate length. Furthermore, this paper demonstrates that the onset of fully-depleted (FD) operation as a function of reverse body-to-source bias is highly sensitive to the channel length.

Published in:

SOI Conference, 1998. Proceedings., 1998 IEEE International

Date of Conference:

5-8 Oct. 1998