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Effect of body-to-source bias on the analog characteristics of 0.35 /spl mu/m partially depleted SOI CMOS for low-voltage low-power mixed-mode applications

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9 Author(s)
Babcock, J.A. ; Nat. Semicond. Corp., Santa Clara, CA, USA ; Francis, P. ; Haggag, H. ; Darmawan, J.
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A 3.3 V 0.35 /spl mu/m CMOS process, implemented on 8-inch bonded SOI wafers, is investigated for low-voltage low-power analog applications. Enhanced low-power analog performance is demonstrated by applying a forward biased body-source voltage which enables reduced short channel effects and a flatter threshold voltage response as a function of drawn gate length. Furthermore, this paper demonstrates that the onset of fully-depleted (FD) operation as a function of reverse body-to-source bias is highly sensitive to the channel length.

Published in:

SOI Conference, 1998. Proceedings., 1998 IEEE International

Date of Conference:

5-8 Oct. 1998