Referenced Items are not available for this document.
In this paper, a modular realization of capacitive threshold logic (CTL) gates is proposed, offering significant advantages in terms of silicon area and speed in certain applications. The generic CTL circuit architecture is presented, its main building blocks are introduced and the operation of the circuit is discussed. A layout design automation environment is presented for the automatic generation of mask-level layout of CTL gates, using conventional CMOS fabrication technology
Published in:
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Date of Conference: 13-16 Sep 1998
- Page(s):
- 281 - 285
- Meeting Date :
- 13 Sep 1998-16 Sep 1998
- ISSN :
- 1063-0988
- Print ISBN:
- 0-7803-4980-6
- INSPEC Accession Number:
- 6161784
- Conference Location :
- Rochester, NY
- Digital Object Identifier :
- 10.1109/ASIC.1998.722997
- Product Type:
- Conference Publications
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