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Datapath library reuse in the design of a high performance floating point unit

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4 Author(s)
Hossain, R. ; Mentor Graphics Corp., Warren, NJ, USA ; Herbert, J.C. ; Gouger, J.F. ; Bechade, R.

This paper describes the use of a datapath library in the design of a high performance, pipelined floating point unit (FPU) macrocell. The existence of the intellectual property (IP) library allowed the rapid completion of the FPU within the context of a high performance structured custom design flow. The 165000 transistor floating point unit was completed in 25 man months from initial customer specification to final physical assembly. The macrocell occupies 2.45 mm×2.55 mm in a 0.35 μm, 4 metal CMOS process and has a simulated cycle time of 5.2 ns at 3.3 V and 85°C

Published in:

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Date of Conference:

13-16 Sep 1998