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RF-to-digital receivers employing bandpass multibit /spl Sigma//spl Delta/ ADC architectures

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1 Author(s)
Pellon, L.E. ; Lockheed Martin Govern. Electron. Syst., Moorestown, NJ, USA

This paper discusses progress in the development of high dynamic range direct conversion digital receivers being developed for DARPA (under the Advanced Digital Receiver Technology (ADRT) program), employing bandpass multibit /spl Sigma//spl Delta/ modulation with a focus on achieving 16 ENOB (98 dB SINAD and 120 dB SFDR) over 100 MHz bandwidth. An electronically tunable loop filter based on Recursive Transversal Filter (RTF) techniques provides bandpass noise shaping with multiple noise shaping center frequencies between 10 MHz and 900 MHz and with multiple bandwidths. A low in-band effective ADC noise figure of 2 dB enables direct conversion without an LNA external to the ADC. In this paper, the architecture for this DARPA receiver, employing 3.2 GSPS HBT AlGaAs-GaAs mixed signal elements, RTF low jitter clock, and 800 MSPSa GaAs DCFL digital processor, is discussed.

Published in:

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1998. Technical Digest 1998., 20th Annual

Date of Conference:

1-4 Nov. 1998