By Topic

Parallel logic level simulation of VLSI circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
R. Bagrodia ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Zheng Li ; Vikas Jha ; Yuan Chen
more authors

Interest in the exploitation of parallelism in circuit simulation has been increasing steadily. In this paper, we study parallel logic level simulation of combinational VLSI Boolean networks using both conservative and optimistic simulation algorithms. In particular, we describe a logic level circuit simulator that uses an acyclic multi-way network partitioning algorithm to decompose Boolean networks and an algorithm-independent simulation language that allows a discrete-event simulation model to be executed using a variety of simulation algorithms. The simulator has been implemented on an IBM SP1 supercomputer and was used to simulate a set of combinational Boolean circuits from the ISCAS85 benchmark suite. Our results show that it is feasible to obtain speedups for even relatively small circuits using both conservative and optimistic methods.

Published in:

Simulation Conference Proceedings, 1994. Winter

Date of Conference:

11-14 Dec. 1994