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Digital CMOS VLSI processor design for the implementation of neural networks using linear wavefront architecture

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4 Author(s)
M. Conti ; Dipartimento di Elettronica, Ancona Univ., Italy ; S. Orcioni ; F. Piazza ; C. Turchetti

This paper presents a digital VLSI implementation of a neural network model using a linear array of processing elements. The pipelined architecture we suggest along with a proper processor design result in a modular and reconfigurable parallel structure capable of high throughput.

Published in:

Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on  (Volume:2 )

Date of Conference:

25-29 Oct. 1993