By Topic

A wavefront array processing architecture for real-time simulation of large scale neural networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Myung Won Kim ; Res. Dept., Korea Electron. & Telecommun. Res. Inst., Daejeon, South Korea ; Youngjik Lee ; Chong Moon Kim ; Yoonseon Song

Describes a scalable parallel architecture for real-time, large scale neural network simulations. Currently the SIMD architecture is largely adopted for implementing digital neurocomputers. However, it is not efficient for simulating large scale neural networks in real-time because of its limited scalability and flexibility. The authors investigate, as a solution, a wavefront array processing (WAP) architecture based on asynchronous communications. The authors compare both architectures in scalability, performance, and flexibility for simulating multi-layer perceptrons. The authors also briefly discuss implementing a high performance digital neurocomputer based on the WAP.

Published in:

Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on  (Volume:2 )

Date of Conference:

25-29 Oct. 1993