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Reconfigurable signal processor for channel coding and decoding in low SNR wireless communications

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4 Author(s)
Halter, S. ; California Univ., San Diego, La Jolla, CA, USA ; Oberg, M. ; Chau, P.M. ; Siegel, P.H.

An area and computational-time efficient turbo decoder implementation on a reconfigurable processor is presented. The turbo decoder takes advantage of the latest sliding window algorithms to produce a design with minimal storage requirements as well as offering the ability to configure key system parameters via software. The parameter programmability allows the decoder to be used in a research environment to study less understood aspects of turbo codes

Published in:

Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on

Date of Conference:

8-10 Oct 1998

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