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Efficient IC design of SC decimation filters

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4 Author(s)
Baruqui, F.A.P. ; Programa de Engenharia Electrica COPPE, Rio de Janeiro, Brazil ; Petraglia, A. ; Franca, J.E. ; Mitra, S.K.

This paper presents the design steps considered in the development of an integrated circuit for a switched-capacitor decimation filter, for practical application in telecommunication systems, for a sampling rate reduction from 48.20 MHz to 16.07 MHz. The design consists of dimensioning the operational amplifiers, capacitances and analog switches, using a supply voltage of 5 V for a 0.8 μm AMS process. Also shown are electrical simulations using SPECTRE and layout detail design. The filter dissipates approximately 46 mW (including the output buffer) at 5 V, and presents a flat frequency response within 0.12 dB from dc to 3.56 MHz

Published in:

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Date of Conference:

30 Sep-3 Oct 1998