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Optimised 0.25 μm high performance retrograde well pMOS device for low-power applications

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2 Author(s)
Swe Toe-Naing ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore ; Yeo Kiat-Seng

The design optimisation, through device simulation and fabrication, of the 0.25 μm retrograde well surface-channel pMOSFET for low-power applications is presented. The high performance pMOSFET is realised by careful design of both the channel and the LDD doping profile. A high transconductance of 190 mS/mm and an off-current of <1pA/μm is demonstrated

Published in:

Electronics Letters  (Volume:34 ,  Issue: 17 )