Referenced Items are not available for this document.
This paper presents a design of an optimized video encoder using a simple pipelined architecture. The proposed video encoder accepts conventional NTSC/PAL video signals. It also processes the PALplus video signal using an improved decimation process. The proposed encoder requires only 25 K gates, which is a 41% reduction in hardware compared with the systolic pipelined architecture of Oh, Choi, Kwon and Lee (see ibid., vol.43, no.3, p.965-71, 1997). The encoder has been designed in a 5-stage pipelined structure to assure stable operation. The overall performance of the encoder has been verified by using 0.65 μm CMOS gate array technology. The chip size is 5170 μm * 435O μm
Published in:
Consumer Electronics, IEEE Transactions on
(Volume:44
,
Issue:
3
)
Date of Publication: Aug 1998
- Page(s):
- 1097 - 1102
- ISSN :
- 0098-3063
- INSPEC Accession Number:
- 6043970
- Digital Object Identifier :
- 10.1109/30.713240
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Aug 1998
- Sponsored by :
- IEEE Consumer Electronics Society
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