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VLSI implementation of the motion estimator with two-dimensional data-reuse

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5 Author(s)
Yeong-Kang Lai ; Dept. of Inf. Eng., Nat. Dong Hwa univ., Hualien, Taiwan ; Yeong-Lin Lai ; Yuan-Chen Liu ; Po-Cheng Wu
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This paper describes the VLSI implementation with a two-dimensional (2-D) data-reuse architecture for a full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates

Published in:

IEEE Transactions on Consumer Electronics  (Volume:44 ,  Issue: 3 )