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VLSI implementation of visual block pattern truncation coding

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5 Author(s)
Yuan-Chen Liu ; Dept. of Comput. & Inf. Sci., Tamsui Oxford Univ. Coll., Taipei, Taiwan ; Yeong-Kang Lai ; Tsung-Han Tsai ; Po-Cheng Wu
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The paper proposes a pipelined architecture of a visual block pattern truncation coding algorithm to minimize the mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for moving pictures

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IEEE Transactions on Consumer Electronics  (Volume:44 ,  Issue: 3 )