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Monte Carlo optimization of superconducting complementary output switching logic circuits

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4 Author(s)
M. Jeffery ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; W. J. Perold ; Zuoqin Wang ; T. van Duzer

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix.

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:8 ,  Issue: 3 )