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Sequential circuit fault simulation using logic emulation

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3 Author(s)
Shih-Arn Hwang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jin-Hua Hong ; Cheng-Wen Wu

A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:17 ,  Issue: 8 )