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Efficient BIST TPG design and test set compaction via input reduction

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2 Author(s)
Chih-Ang Chen ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Gupta, S.K.

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (⩽230) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:17 ,  Issue: 8 )