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Impact of reducing miss write latencies in multiprocessors with two level cache

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2 Author(s)
J. Sahuquillo ; Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain ; A. Pont

In this paper a multiprocessor system with a two-level cache hierarchy is modeled and extensions of two write invalidate snoopy protocols are implemented in the L2 cache controller for coherence maintenance. The paper focuses on the use of different techniques for reducing miss penalty and a comparative performance study is done for each possibility. To solve efficiently a miss read, the early restart technique is implemented in the second level of cache hierarchy and the critical word first technique is used in the first level cache controller. To obtain better performance in the case of a write miss the write allocate technique is implemented at the L2 cache controller. Two models, with different L1 cache controllers are considered in our study, one of them using the non-write allocate technique and the other using the write allocate. We show that the write allocate and non-write allocate techniques are independent over the processors number. The major conclusion of this work is that the non-write allocate technique is not only less complex for implementation but also better in performance if the L1 write miss rate represents a high percentage of L1 miss rate

Published in:

Euromicro Conference, 1998. Proceedings. 24th  (Volume:1 )

Date of Conference:

25-27 Aug 1998