Referenced Items are not available for this document.
A dynamic gate floating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-μm CMOS process
Published in:
Electron Devices, IEEE Transactions on
(Volume:45
,
Issue:
9
)
Date of Publication: Sep 1998
- Page(s):
- 2076 - 2078
- ISSN :
- 0018-9383
- INSPEC Accession Number:
- 6018545
- Digital Object Identifier :
- 10.1109/16.711378
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Sep 1998
- Sponsored by :
- IEEE Electron Devices Society
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