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High-speed CMOS switch designs for free-space optoelectronic MIN's

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3 Author(s)
Kibar, O. ; Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA ; Marchand, P.J. ; Esener, S.C.

We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a two-dimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-/spl mu/m CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 /spl mu/m CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm/sup 2/ and a total power consumption (optics plus electronics) of about 90 W.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 3 )