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Gate-induced drain-leakage in buried-channel PMOS-a limiting factor in development of low-cost, high-performance 3.3-V, 0.25-μm technology

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3 Author(s)
Ghodsi, R. ; Cypress Semicond., San Jose, CA, USA ; Sharifzadeh, S. ; Majjiga, J.

This paper presents a low cost 0.25-μm technology with low standby power for 3.3 V applications. It is shown that as a single gate oxide n-type polysilicon gate technology is scaled, gate-induced drain-leakage (GIDL) in buried-channel PMOS becomes a serious limiting factor in achieving low standby power. The impact of technology choices such as spacer material, spacer width and poly reoxidation conditions on PMOS GIDL is discussed. A technology that successfully limits PMOS leakage is presented.

Published in:

Electron Device Letters, IEEE  (Volume:19 ,  Issue: 9 )