Referenced Items are not available for this document.
The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 /spl Aring/ regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon.
Published in:
Electron Device Letters, IEEE
(Volume:19
,
Issue:
9
)
Date of Publication: Sept. 1998
- Page(s):
- 348 - 350
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 6023673
- Digital Object Identifier :
- 10.1109/55.709640
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Sept. 1998
- Sponsored by :
- IEEE Electron Devices Society
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