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Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

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5 Author(s)
Tsai, Jiunn‐Yann ; LSI Logic Inc., Santa Clara, CA, USA ; Ying Shi ; Prasad, S. ; Yeh, S.W.-C.
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The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 /spl Aring/ regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon.

Published in:

Electron Device Letters, IEEE  (Volume:19 ,  Issue: 9 )

Date of Publication:

Sept. 1998

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