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An 0.8-/spl mu/m n-channel MOSFET with a TiSi/sub 2/-Si Schottky clamped drain-to-body junction (SCDR) and an n/sup +/ implanted standard source structure have been fabricated in a conventional 0.8-/spl mu/m salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n/sup +/-drain/p-substrate/n/sup +/-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n/sup +/ drain-to-p-substrate guard-ring diode connected in parallel.
Date of Publication: Sept. 1998