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A low-power VLSI architecture for full-search block-matching motion estimation

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2 Author(s)
Do, V.L. ; Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA ; Yun, K.Y.

This paper presents an architectural enhancement to reduce the power consumption of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation. Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as well as simulation results on benchmark video clips are presented

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Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:8 ,  Issue: 4 )