By Topic

Subword extensions for video processing on mobile systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jennings, M.D. ; North Carolina State Univ., Raleigh, NC ; Coate, T.M.

Providing video-over-wireless capability to mobile computing platforms results in several interesting challenges. Wireless networks provide less transmission bandwidth than hard wired networks. Because today's wireless local area network technology can provide only around 2 Mbps transmission rates, video compression is essential for transmitting to mobile devices. Due to increased user sensitivity to cost and power consumption, mobile computing platforms prefer a host processor-only solution, opposed to a host processor in conjunction with a digital signal processor. Most general purpose microprocessor architectures have recently extended their instruction set architectures to include parallel instructions for improved performance on multimedia applications, including MPEG (Motion Pictures Expert Group) video. The article highlights the features of several of these extended ISAs for processing MPEG video. Each uses a modified single instruction, multiple data execution model as a technique to enable concurrent execution. In the modified micro SIMD execution model, a single instruction initiates parallel execution on data organized in parallel. The article illustrates the micro SIMD execution of an add instruction. Micro SIMD execution using packed data types (with byte, half word, or word quantities) makes more efficient use of the processor data path for 64 or 128 bit architectures. We refer to this particular form of micro SIMD execution as subword execution

Published in:

Concurrency, IEEE  (Volume:6 ,  Issue: 3 )