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Low power logic synthesis under a general delay model

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3 Author(s)
U. Narayanan ; Intel Corp., Santa Clara, CA, USA ; Peichen Pan ; C. L. Liu

Till now most efforts in low power logic synthesis have concentrated on minimizing the total switching activity of a circuit under a zero delay model. This simplification ignores the effects of glitch transitions which may contribute as much as 30% of the total power consumption of a circuit. Hence, low power logic synthesis techniques which optimize power under a zero delay model are often not successful in attaining "real" power savings as measured under a more accurate general delay model. In practice, to accurately estimate the switching activity in a circuit under a general delay model can be computationally expensive. Hence, to repeatedly call accurate but slow power estimation tools to direct the synthesis flow is not a viable approach in the design of low power synthesis tools. In this paper we take advantage of a fast method for estimating the total switching activity in a circuit under a general delay model to synthesize low power circuits. Specifically, we use the approximation as a basis for algorithms that solve two problems: (1) low power technology decomposition of gates under a general delay model (2) low power retiming of sequential circuits under a general delay model.

Published in:

Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on

Date of Conference:

10-12 Aug. 1998