Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shaditalab, M. ; Dept. de Genie Electr. et Genie Inf., Ecole Polytech. de Montreal, Que., Canada ; Bois, G. ; Sawan, M.

Design and implementation of parallel pipelined Fast Fourier Transform (FFT), using Decimation in Frequency (DIF) algorithm on FPGAs is presented. The FFT core for 1024 complex data point is implemented on the X-CIM which is a Re-configurable Acceleration Subsystem (RAS) with a TMS320C4x DSP-processor and two XC4013 FPGA as its processing units. The proposed FFT machine is an alternative to the bit serial-parallel FFT algorithm using Distributed Arithmetic Look Up Table (DALUT) method. The advantage of proposed design is mainly in its cost effective and hardware-efficient parallel implementations of the N-point DFT, offering highly attractive throughput rates in relation to the conventional DSP processors. Moreover, the processor's data-path structure is independent of sampled data-paints, and it has a self-sorting property where the output is in properly ordered form. Our goal is to improve size-performance requirements of an FFT core function using modular and hierarchical VHDL description combined with IP-core library elements from Xilinx

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998