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Reconfigurable hardware as shared resource for parallel threads

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2 Author(s)
G. Haug ; Tubingen Univ., Germany ; W. Rosenstiel

Approaches to use FPGAs as reconfigurable coprocessors so far always suffered from two problems. First, the hardware required for communication with the host processor occupied an unacceptable large part of the resources available on the FPGA and second, this communication was so slow that the gained acceleration came to naught. The new Xilinx XC6200 family aims to solve both of these problems. The chips are accessed via an SRAM interface, i.e. the host sees them as part of its memory. Besides the configuration bits, which determine logical behaviour and routing, all internal hip-hops of the XC6200 are accessible for reading as well as for writing. This ensures a high performance, since a 32 bit input or output value can be exchanged between the host and the coprocessor by a single load or store operation. In order to make use of the hardware features of the new Xilinx chip series in workstations and PCs easily, a system is presented which synthesizes hardware out of threads coded in C. The threads are part of the C-program running on the host processor. In this paper this system is referred as the Hardware Thread System (HTS). The run time environment required is called the Universal Coprocessor System (UCS). As hardware platform, a specially designed PCI card is used. Besides the reconfigurable coprocessor XC62xx, it consists of the controller (XC4013e) and buffer/data RAM. The RAM of the card can be mapped into the memory address space of the host; nontheless the controller can transfer data between reconfigurable coprocessor and buffer RAM without disturbing the host

Published in:

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Date of Conference:

15-17 Apr 1998